Chip diesize is always critical in chip implementation. Small diesize means small cost for chip.In this paper, different ways to save chip area during implementation are introduced. “Diesize Doctor” is developed to support chip diesize analysis and reduction.“Diesize Doctor” provides two functions to help analyze and reduce die area. One is “Routing Metric” report to evaluate routing-heathy quality. It includes regular metrics (e.g. overflow, hotspot, total wire length ) from Innovus, and newly developed track-utilization utility for routing analysis. With “Routing Metric”, different design databases (e.g. different libraries, netlists, floorplans, tool flows, user setups) can be compared and selected easily.The other function is “Diesize Inspection”. It inspects different chip status and tool options to find potential chip area improve opportunity. The inspections include 1) chip area utilization and routing ingredient analysis, e.g. on-track power stripes, memory/analog channel cost, physical & spare cell cost, low power design cost, clock tree cost, DFT cost; 2) recommended tool version, flow and configuration check; 3) hotspot diagnosis and corresponding suggestions, e.g. padding, corner/channel congestion, unbalanced routing resources, design architecture; 4) other checks such as pad limited reminder, MBFF ratio…Different chip area reduction methods are implemented on 40nm MCUs. The proposed flow is 1) library/metal stack selection; 2) floorplan optimization; 3) power stripe optimization; 4) initial run; 5) chip area diagnoses with “Diesize Doctor.” 6) seek opportunity for smaller size and resolve hotspots.With this flow, smaller chip area is achieved with better area utilization and higher routing efficiency.