In this presentation, we will discuss the criteria, results of our evaluation of Cadence Certus Closure Solution for advanced nodes (7nm, 5nm, 3nm), in context of both Smart Hierarchical large CPU flow and full chip/chiplet timing closure flows. As we deploy Certus for production use on our next-gen Total Compute CPU and GPU cores, we will cover the methodology that can account for scalability and productivity, while maintaining best-in-class PPA.
We will provide information on the benefits of using Cadence Full Flow for our IPs with Genus, Innovus, Tempus ECO/Certus for block-level closure, Certus Closure Solution, Quantus extraction and Tempus Signoff Solution for chiplet/full chip signoff.