In recent years, with the explosive increasement of computing power demand and the promotion of green development concepts, cloud computing centers have a higher requirement for high-performance computing chips, which can perform faster with less power consumption. The power efficiency has become a key criterion of HPC chips. The leading chip design companies have also changed optimization strategy from improving performance to optimizing power efficiency. Power reduction can happen in every process of chip development, in this paper we focus on the power optimization in physical implementation of the high-performance processor core by employing the latest toggle prediction technology of Cadence into the full-flow of physical implementation. Xreplay can predicate toggle rate that is highly consistent with the actual working scene for every optimization flow from RTL to GDS to guide the tool to optimize power. Comparison with the traditional power optimization flow with unified toggle rate and joules-replay power optimization flow, Xreplay power optimization flow can obtain about 6% power consumption benefit. At the same time, Xreplay can generate a simulation waveform which is highly consistent with post-simulation when postroute optimization finishing. After comparison, the power consumption different between Xrelay and post-simulation can reach within 0.5%. Due to no dependence on the long runtime post-simulation flow, the reasonable IR results can be obtained in earlier stage of project, which left more time to get a more robust power ground structure and fix the IR-drop violations.