As the productivity of the digital economy, computing power imposes new requirements on high-performance computing, which stimulates the higher pursuit of chip design. Therefore, higher requirements of performance, power, area and cost (PPAC) are put forward in chip design to meet diverse application demands, which brings design complexity continue to increase. Nevertheless, this causes great challenges for traditional IC back-end design process, such as the need for many experienced engineers and longer time to get reasonable design parameters, due to its high dependency on experimentation and experience during manual iterations. There is no doubt that it becomes a difficult task to achieve the PPAC goal of the project in the limited project period. In recent years, machine learning (ML) technology has shown great potential in chip design. Machine learning can not only quickly generate a variety of layout schemes, but also quickly rearrange major changes to the upstream design. Some advanced agents can efficiently create layouts that have never been done before. Cerebrus, an intelligent and efficient design space exploration platform, has proved this. There are already some successful cases of cerebrus flow applied in PPA improving, which means the chip design with better performance, better power consumption, more optimized area and shorter iteration times are achieved. Here, we introduce cerebrus flow into different process nodes and optimal PPAC is obtained successfully which show the generality of cerebrus flow. Moreover, based on the ML model from first flow optimization in which scenario the best results are gotten, we have tried multi-round and deep optimizations. The results show that adopting ML model as a starting point for next flow optimization can futher enhance PPAC performance. Our results denote that warm start even cold start through ML model from previous optimizing flow is applicable in cerebrus flow which is beneficial to both deep enhancement of PPAC and run timing reducing in chip design.