With the continuous development of machine learning technology, it plays an increasingly important role in the field of chip design. In order to improve the performance, power consumption, and area (PPA) of chips, various new solutions are being explored. This paper proposes a solution based on Innovus machine learning to improve the PPA of chips.This solution learns the cell/net delay from CTS to PostRoute in the chip P&R design stage through supervised learning methods, and fully integrates the machine learning predicted delay into PreRoute optimization, guiding the behavior of Innovus tools in the OPT stage. The advantage of this method is that the machine learning predicted delay can calculate each timing arc (net or cell) and dynamically adjust throughout the entire PreRoute optimization stage. To verify the effectiveness of this method, we conducted a series of experiments, and the results showed that this method performs better in some designs in terms of PreRoute and PostRoute delay/timing correlation, thereby improving chip performance.In addition, we conducted a detailed analysis of this method and discussed its advantages and disadvantages. This method uses machine learning technology to automatically learn delay models in chip design, not only improving chip performance but also saving design time and cost. Dynamic adjustment can optimize chip performance and improve chip PPA. However, this method requires time to train data in order to obtain accurate prediction results. Additionally, this method also requires efficient computing resources to complete training and prediction in a short period of time. Therefore, it may be limited in practical applications.
In summary, this paper introduces a solution based on Innovus machine learning to improve chip PPA. This method uses supervised learning methods to learn the cell/net delay from CTS to PostRoute in the chip P&R design stage, and fully integrates the machine learning predicted delay into PreRoute optimization, guiding the behavior of Innovus tools in the OPT stage. The experimental results show that this method can improve PPA and timing correlation of Preroute and Postroute, thereby improving chip performance. We believe that this method will be more widely used and provide more solutions for chip design.