With the help of Cadence's newly IR Aware Full Flow, the author uses local P/G stripe addition, timing aware IR drop fixing, IR aware placement etc. to avoid and address IR drop issues all through the PR flow. These techniques significantly improve the efficiency of IR drop hot spot fixing and greatly accelerate the convergence of IR drop problems. IR Aware Full Flow saves designers much more time in getting a better PPA result and is of great use to the design process of IC physical implementation.