Success in today's electronics market place,Most SoCs currently being developed have analog or mixed signal blocks, many so-called analog blocks actually have digital-control logic A.Virtuoso-Innovus flow with MS OpenAccess RapidPDK allows for all or parts of the physical hierarchy to pass back and forth between Virtuoso and Innovus technologies easily without having to generate a DEF/GDS file. In this paper, we first describe the way to generate 5nm Rapid PDK, then use this pdk with digital flow to finish 5nm IP design with custom lib. Additionally, this virtuoso-innovus flow provides our analog designers with advanced techniques for 5nm floorplanning, pin optimization, track generation and auto place & routing with RC extraction and timing analysis aware which will simplifies the flow to enable Virtuoso users to run 5nm layout implementation, and also could help us to do full chip STA analysis