With data-centric designs demanding increases in the number of on-chip storage elements, the area occupied by macros and memories has also drastically increased. With the number of rectangular macros going over hundreds, coming up with an optimized floorplan becomes more time consuming for designers. This directly impacts tapeout schedules along with the possibility of leaving some PPA optimization on the table. Through Innovus Implementation’s advanced multi-objective placement technology, the GigaPlace XL engine provides automation to optimize at scale, concurrent placement of macros, and standard cells for multiple objectives like timing, wirelength, congestion, and power. This breakthrough technology provides an innovative way to address design productivity along with design quality improvements reducing weeks of manual floorplan time down to a few hours.