The ENICS SoC Lab at Bar Ilan University tapedout the Israeli HiPer Consortium N16 chip (members include: Mellanox, Ceva, DSP Group, Satixfy, Ceragon, Sonics, others…) and signed-off the design using Cadence’s Pegasus Verification system for all the physical verification checks required by TSMC. Pegasus scaled linearly and delivered ~5.4X faster TAT which allowed the tapeout team to do 2-3 iterations of DRC fixing per day.