Cadence demonstrated its 8-lane controller and PHY subsystem for PCIe at Flash Memory Summit ’23. Watch this video to see how we test the complete multi-lane protocol stack with Keysight’s exerciser and demonstrate electrical performance with Anritsu’s BERT. For more information on Cadence’s PCIe products, visit us at https://www.cadence.com/en_US/home/tools/ip/design-ip.html