Cadence demonstrated its 8-lane controller and PHY subsystem for CXL 2.0/3.0 at Flash Memory Summit ’23. Watch this video to see how we test the complete multi-lane protocol stack with Viavi Solutions Xgig Analyser/Exerciser in 32Gx8 mode. For more information on Cadence’s PCIe products, visit us at https://www.cadence.com/en_US/home/tools/ip/design-ip.html