The LPDDR5X/5 IP products are designed to integrate easily into most applications. The PHY IP can be delivered as either firm or hard macros, supporting multiple floorplan and bump map options. The PHY top-level logic uses low clock frequencies to enable easier, faster, and more reliable timing closure.
The Denali LPDDR Controller delivers a wide array of capabilities to address emerging LPDDR DRAM subsystem RAS, ECC, parity, and data-scrubbing functions. The application-optimized LPDDR5 PHY and Controller can achieve industry-leading data rates, with low-power features that include multiple low-power states for longer battery life and greener operation.