The ever-increasing movement of data from one server to another is taxing the capabilities of network infrastructure today. The industry is quickly approaching the practical limits of electrical I/O performance. As demand for compute continues to increase, electrical I/O power-performance scaling is not keeping pace and will soon limit available power for compute operations. It is possible to overcome this performance barrier by integrating optical I/O directly with compute silicon. Optical I/O has the potential to dramatically outperform electrical in the key performance metrics of reach, bandwidth density, power consumption, and latency. This talk will focus on system performance requirements, recent technology advancements, and the architecture shifts necessary to transition from electrical to optical I/O.

What's missing for a sustainable photonics adoption?

The demand for silicon photonic solutions continues to grow with volumes driven by transceivers for Data Center Interconnect, 5G backhaul/fronthaul, metro/long haul datacom and telecom, and passive optical networks. In addition to these established applications, there is a growing demand to develop silicon photonics for new product applications that include co-packaged optics (CPO), automotive Light Detection and Ranging (lidar), high-performance computing (Artificial Intelligence, Quantum Computing), and infrared imaging and sensing.

To address these markets, GlobalFoundries (GF) has developed a 300mm silicon photonics foundry technology leveraging state-of-the-art CMOS manufacturing processes to monolithically integrate high-performance RF CMOS active and passive circuitry with a comprehensive O-band photonic device library. Key photonic devices include silicon-on-insulator (SOI) and silicon nitride waveguide-based passive components, high-bandwidth Mach-Zehnder modulator (MZM) and Ge epitaxy photodiode, low-loss passive aligned fiber attach, along with RF passives, ESD protection, e-fuse embedded memory, and a standard cell digital library.

This presentation will provide more details on the benefits of the monolithic integration of the RF CMOS along with photonics, focusing on co-packaged optics. These benefits include:

• Reduced parasitics between CMOS and SiPh devices
• Simplified packaging solutions
• Push modulation speed up to 64Gbaud Integrated TIA's and drivers on PIC
• Reduced drive power consumption
• Integrate supporting logic controls on PIC

A manufacturable silicon photonics PDK offering is critical to product companies, from prototyping to mass manufacturing in foundry. CompoundTek has been working closely with Electronics-Photonics Design Automation (EPDA) vendors, including Cadence and Ansys-Lumerical to mature PDKs to mainstream Si CMOS standard.

Delivering 3-sigma statistical support to provide customers with best-in-class PDK models is representative of CompoundTek’s proprietary manufacturing process. The goal was to deliver to the marketplace statistical support with minimal time-to-market, and the company looked for innovative ways to improve its processes for the development and maintenance of PDKs. The 3-sigma CML model-enabled PDK was officially released in March 2021.

This presentation shares an example of customized CWDM wavelength vertical grating couplers to meet the requirements of O-band CWDM commercial customers. Photonic Inverse Design allows CompoundTek to enhance Si photonics PDK offering and create manufacturable designs with minimum feature size enforcement in Ansys-Lumerical shape and topology optimization, layout with Cadence EPDA software, silicon photonics validated in CompoundTek’s Si photonics foundry service (fabrication, on-wafer 8”/12” agnostic testing hub measurement with the commercialization of its new on-wafer wafer-edge coupling technology).

To enable and grow the silicon photonics industry beyond Datacom, there will be application-specific process technologies tailored to sensors, lidar, integrated lasers, quantum computing, etc. All of these different subsets of silicon photonics must be supported by robust design automation infrastructure. At AIM Photonics, this includes:

·       Multiple PDKs for different process technologies

·       Component libraries from different IP providers

·       Customer support, training, and educational outreach

Photonic integration requires vertical optical connections to minimize footprint. Novel vertical couplers are under development at MIT for high-density, wide-tolerance, CMOS-compatible coupling of light with passive assembly. This technology is a key enabler for optical fanout to fiber arrays for Pb/s I/O and heterogeneous integration. We will present current trends in passive chip-to-chip coupling technology with associated design tradeoffs. Automated design software for electronic-photonic packaging will be critical.

Silicon nitride photonics provides capabilities beyond traditional silicon photonics, making it the material of choice for a new generation of advanced optical solutions in telecom, datacom, quantum computing, sensors, and security. In this presentation, discover the monolithic integration of SiN with MEMS and the complete toolbox of optical and electronic packaging in a systems-thinking approach to high-volume product success.

Silicon photonics brings optics to the manufacturing domain of semiconductors. However, photonics packaging and integration still lack manufacturing scalability, limiting its wide penetration to the datacom and telecom industries. We present our Photonic Bump technology which aligns photonics packaging with standard semiconductor manufacturing, packaging, and testing flow. The Photonic Bump enables wafer-level photonic bumping for high-volume photonics packaging, wafer-level testing, and extending of fabless model to silicon photonics.

The digital age is driving a relentless demand for increasing computing power and efficiency. System architectures of tomorrow are being reimagined to clear the current bottlenecks for the most demanding data workloads. The need for higher speed and higher bandwidth interconnect between devices and to the data center network is driving the attractiveness of “co-packaged” interconnect solutions. Launching the high-speed signals directly off a chip package can greatly improve the performance of a channel, but it poses some technical challenges. In this talk, I will discuss the concept of “co-packaging” optical and copper interconnect and the various electrical, mechanical, and thermal considerations for systems designers.

This presentation explains the concept and role of a Process Design Kit (PDK) in the overall design implementation and automation of photonic integrated circuits. This presentation will discuss the enhancement of a silicon photonic physical design in terms of productivity and reliability using the Cadence® Virtuoso® Electronic Photonic Design Automation (EPDA) framework. We introduce a schematic-driven layout (SDL) methodology for photonic design and explore its connection to a physical design’s representation.

As ubiquitous photonic components, we will use photonic waveguides to demonstrate algorithms, methodologies, and flows in this presentation. We will establish the waveguide template concept and its relationship with a technology file and explore the need for different types of primary waveguide devices. We will also discuss use cases of different waveguides, evaluate the need for different waveguide connectors and waveguide routing options, and demonstrate the implementation of an interactive waveguide router and its use cases.

The presentation includes a few examples using the Virtuoso CurvyCore engine to implement different types of waveguides, and introduce new concepts such as facets, path, surface, and so on, and their use in parameterized cells (PCells) implementation. We will examine features provided by Virtuoso CurvyCore's mathematical engine to enhance the reliability of our physical design and PCells.

Light has long been acknowledged as an ideal transmission modality for high-bandwidth communications, partly because of its lack of parasitic environmental coupling. This allows us to branch, split, and route it to an almost arbitrarily large network topology. We believe this will be crucial to the development of large and eventually brain-scale artificial intelligence systems. Therefore, we seek to demonstrate foundational integrated opto-electronic hardware capable of leveraging this tremendous advantage. Unencumbered access to the third dimension will be crucial in achieving sufficient routing and fan-out for complex AI. In this presentation, we present our group’s recent experimental and theoretical work on multi-planar integrated photonics, and discuss the various needs and solutions from the ground up:

* Platform development – The consideration of photonic materials for best performance; the design of multi-planar stacks to achieve optimal density of connections and interplanar couplers with high performance.

-- Routing networks – Design and implementation strategies to achieve integrated photonic waveguide networks, as well as the experimental demonstration of highly accurate and arbitrarily specified optical power distributions. 

- On-and-off-chip coupling – Realistic photonic networks for AI will use monolithic wafer real estate to the fullest extent; however, they will eventually require longer-distance connectivity to adjacent nodes to increase the efficient use of spatial volume. We will discuss recent work from our group on highly efficient and low-profile fiber-to-waveguide edge couplers for breaking light out of the chip or wafer.

>> The future of multi-planar photonics – To conclude, we consider future research directions that will enable opto-electronic artificial intelligence networks of increasing scale.

> The future of multi-planar photonics – To conclude, we consider future research directions that will enable opto-electronic artificial intelligence networks of increasing scale.

For a typical photonic integrated circuit (PIC) design, designers use a combination of silicon-validated components from a process design kit (PDK) and custom components that adhere to the foundry process design rules. However, as layout and simulations for a custom photonic component are typically handled with different design tools, designers usually need to duplicate the component geometry on these tools, which is both inefficient and error-prone. To facilitate custom photonic component designs, this work demonstrates a direct integration between the Cadence Virtuoso Layout Suite and Ansys Lumerical multiphysics simulation tools through the Cadence Integrator Toolkit Database (itkDB). The integration allows users to design their photonic component layouts in Virtuoso Layout Suite, efficiently import the same layout geometries and pins to Ansys Lumerical multiphysics simulation tools and simulate it accurately with the layer stack information from the foundry. This workflow saves significant effort in checking layout consistency, accelerates design iterations, and ultimately reduces production costs.

Questions asked during the event are answered by the speakers and panelists.

Applications such as autonomous driving, datacom, sensing, and computing are driving demand for silicon photonics technology. In this presentation, we will highlight how pure-play foundries are enabling fabless PIC design teams to design products with improved bandwidth, sensing capabilities, and reduced power consumption of photonic devices by providing both standard and customized process technologies and design platforms.