Use this education kit to teach the different technologies and methodologies for verification and to work on practical exercises verifying designs.

Kit Specification

  • Summary: This set of 11 modules with lecture slides and lab exercises (in selected modules), plus videos, is ready for use in a typical semester (full syllabus below).
  • Modular and Flexible Use: Educators can choose the modules to teach—use all the modules in the Education Kit or only those that are most appropriate to your teaching outcomes. All provided materials are editable and can be easily adapted for the educator’s needs.
  • Recordings: Videos can be used for self-study of the subject.
  • Level: Intermediate. Students are required to have a basic understanding of chip design and Verilog

 

All software tools required for the practical part are available through the Cadence University Program. In order to become a member of the Cadence University Program, please write to universityprogram@cadence.com for assistance.

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Course Aim

To explain to students the different technologies for verification and to give them practical exercises on how to verify designs.

Learning Outcomes

Knowledge and understanding of

  • Which verification technologies exist
  • Which verification technology is most appropriate throughout the design stage
  • Verification aspects of SystemVerilog
  • Universal Verification Methodology (UVM) and verification environment
  • Details of static, formal, dynamic, and emulation verification technologies
  • Planning of verification and verification coverage
  • Debugging of verification results

Syllabus

No. Syllabus/th>

1

Introduction to Digital Chip Design Development Flow

2

Verification Types Through Development Flow

3

Unit-Level/Subsystem/Full-Chip Verification Methodologies

Cadence Verification Suite

4

Introduction to SystemVerilog

5

Introduction to UVM (2 parts)

6

Introduction to Static Verification

7

Introduction to Formal Verification +

Introduction to SystemVerilog Assertions

8

Introduction to Dynamic Verification

9

Introduction to Emulation

Overview of Cadence Palladium

Overview of Cadence Protium

10

Debugging Tools

11

Introduction to Power Verification