Cadence technology has been enabling to a “life cycle” of graduate teaching and research on digital IC implementation at UCSD. This talk will describe this “life cycle” and how it has given rise to recent research on advanced-node implementation methodology and EDA technology. Three examples: (1) enablement of machine learning in IC design, (2) advanced-node models and methodologies in physical design, and (3) RTL generation (for ASIC hardening of machine learning algorithms and architectures) that predictably meets PPA targets at the end of IC implementation.

During the Spring 2020 semester at the University of Notre Dame, we offered a High-Level Synthesis (HLS) course where students studied the hardware and software aspects of integrating heterogeneous components into a complete system; evaluating designs in a multi-objective optimization space; and designing new components that are reusable across different systems, product generations, and implementation platforms. The course was divided into a Principles Track and a Practice Track. Topics under the Principles Track included the synchronous model of computation, System-on-Chip (SoC) platforms, latency engineering, dataflow process modeling, frameworks for comparing models of computation, latency insensitive design, modeling concurrency, and performance analysis with Petri Nets. In the Practice Track, students gained familiarity with the SystemC programming language, Cadence Incisive and Stratus for Synthesizable SystemC, processes and events, Transaction Level Modeling, multi‐core SoC architectures, and bus‐based on‐chip communication architectures, and HLS of Accelerators in Embedded Scalable Platforms. As most universities elected to do as the result of the COVID-19 pandemic, the University announced a move to online learning. Professors and teachers across the country had to rapidly adapt their courses to an online or asynchronous approach. In the HLS course, one of the final projects was going to involve FPGA prototyping. Since the students would no longer have access to Xilinx Zynq boards appropriate for SoC synthesis, the final project had to be scrapped and replace. This course was part of a pilot study with Notre Dame, Cadence Design Systems, and CMC Microsystems, where a Cadence license was installed and hosted on an Amazon AWS EC2 cloud-hosted web service to construct and administer the Cadence Design Systems applications without the need for any additional hardware. When the course moved online, we were able to avoid many challenges faced by universities forced to conduct remote sharing of the student servers through virtual private networks. As a result of this framework, students were able to complete a robust final project that would not have been possible using a conventional Cadence Academic license put on a student server. They were able to train and synthesis a Convolutional Neural Network for pattern and image recognition using Tensorflow to obtain the weights and biases for convolution, pooling, and matrix multiplication. Then, using Cadence Stratus, Xcelium, and Genus Synthesis Solution, the students were able to synthesize the framework down to an ASIC using the Cadence Generic Process Development Kit for 45nm.

The level of automation of a vehicle is the key driver of the E/E architecture and the electronic content of a car. It’s obvious that future cars will be equipped with more computing power, AI-based systems, car-to-car communication technology, high-bandwidth Ethernet networks, and digital cockpits. Radar, Lidar and Camera are the key sensors to enable fully autonomous driving. However these sensors still need to be significantly improved in terms of resolution, power consumption, safety, form factor and cost but will also evolve to address new compute architectures.All these new technologies will dramatically increase the complexity of electronic systems which require to integrate more functionality on a chip, rather than on a PCB to provide the performance, safety and reliability in a small form factor device. As a result, a new class of high-performance System-on-Chip (SoC) and/or System-in-Package (SiP) is needed to process all sensor data and fuse them together to enable vehicles to become “aware” of their surroundings.While some high-end automotive SoCs have been already designed in 7nm some companies are preparing already their next-generation process technology at 5nm. Foundries claim that 5nm provides about 20 percent faster speed or about 40 percent power reduction and is perfectly suited for the next generation of automotive processors. Cadence's Automotive solutions can help you to enable such highly integrated systems that can make cars safer and more reliable. This talk provides an overview on automotive trends and the implications for SoC and System enablement for Sensors and Advanced Driver Assist Systems (ADAS).

As the safety level of autonomous driving increases, the computing demand for an automotive perception SOC also rise sharply. Solving the PPA challenges of such large scale SOC design while meeting functional safety requirements is the central focus facing the industry. In this paper, BST presents a 16nm SOC with heterogeneous computing architecture to address the challenge. It is demonstrated by combining in-house designed hardware engines with industry proven DSP IP from Cadence, an automotive perception computing platform can deliver flexibility, scalability and real-time high performance at very low cost.

As ADAS evolves to autonomy, Arm has prioritized and simplified safety without compromising security, performance and
power-efficiency in general automotive and autonomous-class processors.
In this presentation, we will first introduce Arm's latest AE (Automotive Enhanced) processor with safety innovations
and the autonomous-class compute complex subsystem that can embed up to 64 of these processor cores, enabling partner
designs targeting ASIL D.
We will then discuss the architectural feature differences between Arm baseline vs. AE CPUs in general, moving on to
focus on Cortex-A76AE core and the corresponding Automotive Enhanced DSU.
The bulk of this presentation will focus on physical implementation of the Cortex-A76AE processor core using advanced
features of Cadence RTL to GDS2 digital implementation tool chain in 7nm:
1. core pair implementation using Stylus flow
2. clock and reset implementation
3. timing constraints organization
4. floor plan
5. placement guidance based on processor data flow
6. power intent strategy
7. asynchronous bridge implementation supporting split-lock operation
8. PPA trade offs considered
9. future developments

Wireless communications and mm-wave radar systems enable next-generation vehicles with a host of functions, ranging from safety and navigation features to infotainment and remote entry/control. Along with the deployment of 5G ultra-reliable low latency networks and its potential to support autonomous driving, automotive connectivity also includes GPS, Cellular, Dedicated Short Range Communication (DSRC) / V2X, Satellite Digital Audio Radio Service (SDARS), and more. These systems require a host of enabling technologies including:
•high-density dashboard electronics 
•wireless sensing/communications 
•integrated antennas for automotive-oriented mobile telecommunication services and on-board electronics systems
•mmWave, beam-steering antenna arrays for automotive drive-assist systems (ADAS).
Developing these systems requires specialized simulation/measurements, high-frequency device models and design automation found in RF/microwave electronic design software from Cadence AWR.  This talk will look at several case studies where RF/microwave engineers have used design software to address a range of design challenges in developing high-frequency components and systems for various automotive applications and supporting antenna systems. For ADAS systems, a design example will show how system, circuit and EM tools combine to support mm-wave FMCW (frequency modulated continuous wave) automotive radar with active phased array antenna development. Other case studies include a wireless tire pressure sensor, LNA design for an SDARS receiver, and an EMC simulation of an automotive navigation/audio system.

With the rapid growth in design complexity and demands of leading process nodes, the compute and infrastructure needs for next-generation designs pose new, daunting challenges. That’s why every high-performance team is looking at Cloud with great interest. The scalability and agility offered by cloud addresses many of the gaps in design infrastructure. However, transitioning to cloud requires thoughtful decisions about cloud architecture, data management, infrastructure setup, security, to name a few.

In this session, we discuss the pros and cons of various cloud architectures, their suitability for design flows and IT needs for successful cloud transition. We also describe the Cadence Cloud solutions used by over 100 customers to successfully embrace cloud for their production designs.

CadenceLIVE 2020: Scaling Semiconductor Design Workflows on AWS

Device level pattern planning, placement and routing of the matched structure is an important phase of full custom analog layout development. Matched devices are extensively used in analog designs, such as differential amplifiers and current mirrors. The matching performance achieved is crucial ingredient to ensure the specifications. According to the criticality of the matching performance different matching techniques are required depending upon the number of devices and layout area available. Quality matched structure primarily requires compact layout and gradient cancellation. For gradient cancellation, structures require pattern visualization and pattern visualization is becoming complex for devices mapped in more than 4-6 rows. In semi-custom already implemented or legacy designs, a placed and routed pattern might be present more than once. Designer can save these patterns as “template” and re-use these patterns to generate the similar style matched placement pattern quickly, instead of starting from scratch. Also, patterns are user configurable, stored in pattern database and can be loaded for reusability. In core analog blocks approx. 40-60% devices required to be matched. These devices are preferably matched in common centroid techniques. In this paper, layout re-use methodology, different visualization techniques and ModGen topology editor interfaces have been discussed for quick matched pattern planning, placement and routing.

AMS design challenges have significantly increased with complex design specification requirements at advanced CMOS processes. The Samsung 3nm Cadence AMS Design Reference Flow is intended to reduce design complexity and improve productivity at 3nm technology nodes by demonstrating how Samsung foundry PDK’s are well in sync with the latest Cadence design tools. Samsung Foundry customers can take advantage of the most advanced features for circuit design, performance, reliability verification, automated layout, block, and chip integrations for custom and digitally-controlled analog designs based on the Cadence Virtuoso and Spectre platforms. Learn about the Reference Flow, from schematic to layout verification and the future.

EDA tool runtime (expressed as turnaround time, or TAT) does not scale linearly as design size grows. Furthermore,
all EDA tools have a design-size limit, usually expressed in terms of instance count. Even with the best parallel-processing algorithms,TAT becomes excessively long for 10M+ instance designs, causing time-sensitive design teams to try and break up their designs into more manageable sub-blocks; by completing each sub-block independently and in parallel, runtime can be significantly reduced.

However, when it comes time to re-assemble the design at the top level, differences in I/O delays and clock tree construction between sub-blocks can create timing closure headaches during final integration.

By using Cadence (Tensilica's) DNA100 neural-network accelerator subsystem as an example, this presentation will illustrate a novel constraint method for bottom-up design using Extracted Timing Models (ETMs) for certain sub-blocks. This 15M instance design is too large for a P&R tool to process in a single shot; however it has a design hierarchy that can be easily partitioned: one Vision P6 (VP6) processor acting both as a control core and an offload processor, plus four identical compute + memory computation super-blocks (SBLKs).

In parallel, the VP6 and SBLK were each taken through a high-performance Genus --> Innovus --> Quantus --> Tempus design flow; as a last step within Tempus, an ETM was generated for both the setup and hold corners of the design; this ETM is effectively one large macro cell expressed as a Liberty timing model; along with an abstract LEF file generated in Innovus and an abstract scan model generated in Genus, both the VP6 and SBLK can now be treated as bits of IP, just like a memory macro instantiated in a design. This allows the final top-down assempbly flow at the subsystem level to proceed far faster, as now the top-level instance count consists of four SBLKs and a VP6, along with all the remaining glue logic.

However, there is a problem with the Liberty model of the ETM - for the boundary ports, there is no distinction made between logic delayand clock insertion delay; the top-level timing engine only sees a combined value. For example, say a large sub-block such as SBLK has a median clock insertion delay of 700ps. Further assume an input port has a port --> logic --> capture_flop_setup delay of 300ps, and anoutput port has a launch_flop_clk_to_q --> logic --> output_port delay of 400ps, from the timing analyzers perspective at the top-level
using standard ETMs, the input port setup delay is -400ps, while the output delay is 1100ps. This causes havoc for both setup and holdfixing at the top level.

The control software for a safety criticial control module should never lose the tread of control. ISO 26262 describes many kinds of "processor sequence monitors" that can be applied to help detect a control software flow error. The Windowed Watchdog Timer has a low cost in implementation cost, but is rated as "medium high" in its ability to catch program sequency failures. Customers may implement their own WWDT, or may use the WWDT integrated with an Xtensa Certified ISO 26262 Processor of DSP

DSPs and Processors process a lot a data and can generate a lot faults and every Functional System systems needs some kind of fault monitor.  Some of the faults are "aware", but some faults not detected by the processor. Also, many faults can be safety ignored, while some indicate a fatal fault calling for a reset. Given the complexity of these system, this is not one off-the-shelf fault monitors system useful.  This presentation cannot therefore present your with a fully formed solution, but it will review the categories of faults you will encounter, the ways they are typically handled, and their importance to ISO 26262.

What is it? ... Why do I need it? … When will I need it? … How do I use it? One of the hottest trends in semiconductors today is “chiplets”.  It makes sense though…the semiconductor industry has been and is still obsessed by Moore’s Law.  As the advancement of the shrinking transistor has slowed (the concern that Moore’s Law is finally coming to an end), the need and desire to develop bigger and larger chips has increased.  Talk about moving in opposite direction.  So, how do we reconcile this pulling in different directions?  Instead of designing these monstrous monolithic chips in a single die, the semiconductor industry is moving to designing and developing chips into smaller and more specialized/optimized blocks (chiplets) that can be “easily” connected to increase computing capability, provide more functionality, increase yields, and leverage multiple process nodes, thus lower costs and preserving the spirit of Moore’s Law.

Efinix is a global company working to provide the next generation of programmable logic devices based on its disruptive Quantum architecture.  Even though the Efinix fabric is both process and fab agnostic, there are still challenges to achieve first-pass success in deep sub-micron process nodes down to 10nm.  The small Efinix design team was able to achieve our success with our Cadence partnership by using both the custom and digital design flow.  Our design methodology utilizes Virtuoso for custom design and layout, Spectre and Xcelium for simulation, Genus integrated with Innovus for synthesis to implementation, Quantas for extraction, Voltus for EM/IR signoff, and Pegasus along with DFM tools for smooth tapeout signoff to foundry.

Embedded Memories are essential part of NAND Flash CMOS chips for running the NAND algorithm operations. With changing process and design rules Embedded memory blocks need to be characterized robustly to meet the more rigorous technological requirements. These blocks need to be characterized with timing, power, capacitance, noise, etc. data to be used in synthesis and PnR stages of design. Liberty models (.libs) are generated with specific timing arcs defined by the designer based on functionality of the block and the logic interacting with the embedded block. Traditionaly design has been following QTM based approach to generate the .lib models which uses some set of commands to define the timing arcs in a simplistic fashion. The method comes with a benefit of being easy to maintaing and quick to generate where designer feeds in data from analog simulations. But this method sees bigger cons in terms of running simulations at cross corners and extracting data in time consuming and prone to manual mistakes. This puts the burden completely on the design to provide accurate data for all the specified timing arcs. Another drawback being that the .lib is generated with 1x1 lookup table only and with inaccurate input cap and power values. This may result in extrapolation by the synthesis and PnR tools which could lead to adding extra logic and inaccurate timing analysis. Need for a tool to replace this highly manual and data short method is highly desired to save designer's precious time. Liberate MX helps solving these problems in a very clean and accurate fashion. Especially the Dynamic characterization feature which speeds up the process still giving full control to the designer. Designer only needs to specify the timing arcs and vector tables, which tool uses to generate the timing and cap values against any size of lookup table and can be run accross several process corners. These values can be verified by taking the simulation setup auto-generated by the tool and running with any desired simulator.
The new method not only eliminates the cons faced by the traditional method but also provides extra set of tools to generate data from the embedded memory blocks and be characterized close to standard cell format. The method helped reduce the characterization for these custom blocks from several weeks to few days and eventually an overnight job once methodology established.

Handing off RTL IP demands a high bar to know what the final physical realization will look like from a power, performance, and area (PPA) perspective. Total confidence in silicon performance prior to customer engagement is critical. For these reasons, we’ve engaged with the new Genus iSpatial flow – improved predictability of physical results, and superior PPA. We’ll discuss the switch from our legacy synthesis flow to Genus iSpatial – including Common UI and Early Clock Flow, and how it’s improved our designers efficiency and end quality of RTL that we deliver to customers, with examples from our latest N7 designs.

The Neural Engine is an on-chip hardware designed to run deep neural networks at high speed and low power with accuracy, enabling devices to respond to real time. From self-driving cars, to the detection of cancer, AI is everywhere. 

In this paper, we present an efficient model for implementing high performance low power Neural Core using Cadence’s digital implementation flow. Our design was 19mm2 Neural Core which used 20 Deep Learning Processing Units, 2 high definition compressing units. It runs multiple imaging/vision application pipelines simultaneously, with the flexibility of 16 vector processors optimized for vision workloads. The design has centralized on-chip memory for higher bandwidth which minimizes latency and power. Synchronous architectures increase complexity for implementation. A crisscrossing data flow topology and the loopback control increases complexity. With our Implementation we were able to boost frequency by 15% and reduce total power by 10%.

The implementation model relies on evaluating design closure parameters at early stages in RTL/Implementation. Design planning started with carefully carving out modules as partitions and selecting aspect ratios to fit in the SoC. It involved coming up with module guides to help data flow, along with appropriate path-group optimization and ChipWare Selection. Implementation starts with carefully selecting lib cells at synthesis, planning for pipelines, and running optimization. For wire dominated designs we needed a rich library with multiple flavors of complex cells to help reduce logic depth. Carefully flattening key hierarchies helped in improving area. Based on physical synthesis, the model required us to fine tune our path group and ChipWare selection while focusing on Critical module optimization. This model also relies on 2-Pass placement, the second pass enables incrementally passing on higher weight for critical modules. Our Flow Optimized power by doing activity analysis, and enabling power driven design mapping, placement and optimization. For clock construction, we enabled wire delay-based implementation. We biased clock delay inside partitions to match wire delay at chip level which helped in reducing hold violations. The model uses opening of limited skewing and faster cells on deep and unbalanced paths after a round of optimization giving flexibility in design convergence. For improving dynamic power, flow uses multibit Optimization, enabling maximum and greedy MB % at synthesis and eventually toning down during implementation. The model additionally uses path-slack based optimization during implementation which further helped improve power and timing. 

With a blend of Cadence’s implementation tools and our development model, we improved predictability and turnaround time during convergence cycle along with meeting QoR metrics with performance, power and area gains.

The Cadence digital implementation tool, Innovus, continues to extend technology innovation to ensure designers can complete ever larger and more complex designs. During this session Cadence will share the latest Innovus 20.1 release and 2020 roadmap technology highlights. Topics such as physically aware logic restructuring, advanced hierarchy flows, and machine learning will be discussed, all resulting in improved power, performance and area (PPA).  Attend this session to learn what the next phase of Innovus Innovation delivers.

This presentation will give a high level overview of the Tempus Full chip ECO feature and our quality of results.

In 2018, we found that Tempus ECO was struggling to run at the chip level or with large hierarchical partitions.  We were looking for something that could handle the data volume of 50-100M instance designs.

Cadence worked with us to roll out their “Full Chip” eco beta feature.  This feature uses abstraction of the design to reduce the data model.  Only the areas of the design with timing problems are kept in the data model.

We found this feature gave us a 3.75X reduction in peak memory and a 5.8X reduction in runtime on a 100M instance chip design.  We also have found significant runtime reduction on large partitions around 15M instances. Quality of results met our expectations and will be covered in the presentation.

We also have used the Tempus power optimization features on these designs.

“Full chip” eco allows us to be more aggressive in our leakage optimization at the block level.  Leakage optimization on boundary paths may cause some timing fallout due to optimistic constraints.  The Full Chip eco feature is able to easily recover the timing of those boundary paths.   Using this technique, we were able to save 20% leakage versus our previous 9% leakage savings.

Samsung have been collaborating with Arm and Cadence to develop an optimized 5nm implementation flow. Samsung will show how the benefits of the 5LPE process node can be utilized to meet high-performance and low-power goals on the latest Arm CPU. Techniques such as Genus/Innovus iSpatial technology, Machine Learning & IR-aware optimization, and final signoff-driven design closure will be discussed, all based on the integrated RTL-to-GDS Cadence physical synthesis flow. This remarkable flow is available to customer as a Rapid Adoption Kit so designers can benefit from Samsung experience.

Two issues with mixed-signal simulation have nothing to do with the design itself. The first problem is the performance of the analog solver, which often weighs heavily on the overall simulation time. The second is the ability to adopt the latest release of a digital or analog solver because the AMS integration of the two often lags, sometimes by months, preventing customers from taking advantage of the latest fixes. Well, good news. Cadence has solved both issues with the release of two products: Spectre X Simulator for the analog solver and Spectre AMS Designer Flex Use Model, allowing users to combine the latest analog and digital solver releases when they want. In this session, we will discuss how to take advantage of Spectre X Simulator within Spectre AMS Designer for better mixed-signal simulation performance and to take advantage of the latest updates in both Spectre X Simulator and Xcelium Parallel Logic Simulation.

Analog blocks within mixed-signal designs are generally black-boxed when it comes to static timing analysis (STA). To include these blocks, they must be first characterized independently to generate liberty (.lib) files; then, the timing information can be rolled up to the IP/SoC level for STA. Traditionally, tools used for standard cells and memory blocks have been reused for analog block timing characterization. The complexity involved in tuning these tools to suit the analog blocks, along with their inability to handle complex analog structures, resulted in long turnaround times and inaccurate data.  This created a need to adopt a tool that runs from an analog simulation cockpit while creating .lib files. This presentation covers the benefits of this flow and common use cases. 

Currently, there is no dedicated plan-based verification methodology for analog and mixed-signal verification.  Cadence vManager and vPlanner technologies have been used by digital design engineers to perform digital verification. There is a trend to run top-level mixed-signal verification using vManager Verification Management. However, vManager technology requires regression setup time and scripting skills. Learn how Cadence Virtuoso ADE Verifier closes the gap with spec-driven verification for analog circuits.

Semiconductor companies provide their customers with complex design guides to successfully design-in their ICs. These guides are targeted for all kinds of design configurations – multiple layer counts, multiple topologies, etc... For complex design collateral the end user needs to determine which of the rules apply to their design and then convert them to design constraints. This process is very manual and requires a substantial effort.  Intel has a user interface tool to allow them to input design parameters that tailors the design collateral for that specific design.  Given that the customer will set the tool up for their specific design; the information can be then setup into a set of electronic files representing the design   Intel has developed a new solution working with Cadence, and one other EDA vendor, to accelerate the creation a set of electronic constraint files for a specific target design. These constraints can be consumed by either of the EDA vendor tools. This paper will show how Intel Platform Design Studio can shorten days, even weeks of time to a few hours to create electronically consumable constraints.

Rigid-Flex PCBs have been used in many modern electronic devices (such as mobile phones, laptops, and wearables, among others), due to their form factor, light weight, and cost-effectiveness. Electromagnetic (EM) analysis of Rigid-Flex PCBs has always been a challenging task for many commercially available 3D numerical solver technologies (FEM and FDTD), due to the complexity in the 3D designs. Much of the complexity comes from bending of the board into small spaces and usage of hatched ground and power planes. In this paper, we first address the key challenges faced by the EM engineers and then propose a novel automated simulation workflow for a fast-to-market product development process. The proposed workflow, utilizing Cadence® Allegro® PCB Editor and Clarity™ 3D Solver, is the first of its kind in the PCB-EM community. Compared to alternative, highly manual processes, this flow is less error prone and very efficient in setting up the design for EM simulation. In addition, it runs faster than the other legacy 3DEM tools in the industry.

80% of the Printed Circuit Board (PCB) cost is established early in the design stage. The physical envelope, electrical, thermal, assembly, reliability and interconnect strategy predominately impact the cost. Rigid, flexible and HDI cost models significantly differ. Minor adjustments to the requirements can significantly affect the final cost. Once the layout is complete it is extremely difficult to perform significant cost reduction. Each fabrication facility’s equipment and process structure and technical capability impact the manufacturing cost. It is very important to match the design attribute technical requirements to the production capability and business model. This presentation discusses high level general manufacturing cost models and the key technical cost drivers. Understanding these relationships will aid in determining when to push the manufacturing technology envelope to meet specific technical requirements.

Cadence®  AWR Design Environment® platform is a simulation platform for microwave and RF engineers. It is well suited for the design of RF filters and power amplifiers. Learn the key features of AWR Microwave Office® circuit simulator, part of the AWR Design Environment platform. See how this RF/microwave design platform differs from and complements Cadence Virtuoso platform and Virtuoso RF Solution. Step through the design of a distributed, planar filter in a typical RF PCB and an RF amplifier in a GaAs chip technology. These examples illustrate critical concepts and features of the software:  

• Harmonic balance frequency domain circuit simulation technology contrasted with time domain simulation methods seen in analog design
  • Synthesis tools for filter creation and matching networks to loads
• Emphasis on interconnect modeling in the circuit and close coupling between the model and the layout
  • Electromagnetic simulation of the circuit is commonly performed for reasons of verification of the models and checking unintended coupling between different parts of the layout

Wireless communications and radar systems enable next-generation vehicles with a host of functions, ranging from safety and navigation features to infotainment. These systems require enabling technologies including wireless sensing/communications, integrated antennas for mobile telecommunication services, and mmWave, beam steering antenna arrays for automotive drive-assist systems (ADAS). Developing these systems requires specialized simulations, high-frequency device models and design automation found in Cadence® AWR® RF/microwave software. Learn through case studies how to address design challenges in developing high-frequency components and systems for automotive applications and supporting RF to mmWave front-end systems.

5G New Radio (NR) networks represent the next milestone in enhanced mobile communications, targeting more traffic, increased capacity, reduced latency and energy consumption.  To achieve 5G NR performance targets, these communication systems must improve spatial efficiency using multiple-in/multiple-out (MIMO) and beam-forming antenna arrays while adopting more spectrum to increase bandwidth. Learn about design challenges in developing high-frequency components for 5G NR communications - from beam-steering antenna arrays to mmWave MMIC power amplifiers using GaN semiconductor technology. Review typical 5G NR system requirements, learn how they impact component performance specifications and physical implementation with case studies on overcoming design and integration challenges using RF/mmWave simulation software.

RF engineers confront a myriad of challenges to bring their designs to life. From the ability to verify a complex 5G or automotive standard, to running electromagnetic (EM) analysis across chip, package, and board, or to simply verifying RF module connectivity, these challenges can overwhelm traditional EDA design flows that are notoriously fragmented by using multiple vendors.

Safety and Security are fundamental requirements in today’s complex designs. However, they are often the final requirements to be signed off before a design can be released to market – creating a long pole in the product design process.  Green Hill Software provides products and services that enable their customers to solve the most difficult problems in embedded systems. And Cadence technology can be used to assist the customer in addressing the hardware security challenge. Green Hills will discuss how their unique expertise in achieving the highest levels in safety and security, while also maximizing programmer productivity can be combined with Cadence’s Shift Left strategy and Tensilica cores for a compelling solution that exceeds requirements for the military, automotive, avionics, medical and industrial markets.

FAST is known for working on some  of the world’s most challenging advanced node SoC programs.  They provide a scalable set of capabilities from architectural exploration to sign-off.  As hardware security has become a first order priority in electronic products, FAST has been charged with creating the fundamental ingredients of secure hardware design.  This paper will outline the FAST HSM silicon proven solution and roadmap that includes hardware root of trust (HROT) core, crypto accelerators, true random number generator, secure debug authentication and more. The paper will discuss the challenges in delivering the RTL and software solution.

Dover Microsystems' CoreGuard technology is the only solution for embedded systems that prevents the exploitation of software vulnerabilities and immunizes processors against entire classes of network-based cyberattacks. CoreGuard acts as a bodyguard to the host processor, monitoring every instruction executed to ensure it complies with a defined set of security, safety, and privacy rules. If an instruction violates an existing rule, CoreGuard stops it from executing and issues an alert, before any damage can be done.
In this presentation, Dover and BAE Systems, will demonstrate how the CoreGuard-protected Tensilica core can stop a cyberattack on an Aerospace and Defense system. We will show how CoreGuard can issue an immediate alert, enabling the system to take a defensive response in real-time. For example, in the case of a drone, the response could be to activate an alternate, “safe” application where the device would stop listening to the network and pull an encrypted GPS location from memory. 
In addition to a specific attack example, we will also cover the basics of protecting an embedded processor, as well as the challenges and solutions around integrating CoreGuard with the Tensilica architecture.

In this session, we will discuss how to use Xcelium to make randomized regressions faster, how to monitor on-going regressions and identify how randomization influences coverage of the regressions.  Also discussed is how to produce more efficient regression that maintains coverage while reducing simulation cycles up to 5 times. We will examine other potential benefits and real results using Xcelium simulator.

To verify the state-of-the-art InfiniBand and Ethernet interconnect solutions and to accelerate time to market, Mellanox created a scalable emulation environment that enables early hardware/software co-verification and pre-silicon system-level performance validation. This emulation environment is based on Cadence Palladium platform and allows Mellanox’s design team to deliver industry leading interconnect performance.

If the input of a combinational circuit changes, unwanted switching variations may appear in the output. These variations occur when different paths from the input to output have different delays. These switching variations can cause spurious pulses that may cause undesirable consequences to the circuit and thus are called hazards. Unless these hazards are eliminated, improper operation of the circuit may occur. This paper describes the novel approach of detecting logic hazards in combinational circuits through the use of formal methods. First, hazards in a combinational logic circuit resulting from simultaneous changing of two or more inputs are discussed. Second, the novel method of detecting the hazards is presented.

The interaction of hardware and software in Systems On Chip is complex and will affect both the functionality and the performance of the final design.  Therefore it is important to present consistent debug and analysis solutions across all stages of the design process.  In this presentation we will look at how Arm and Cadence have co-operated to provide such solutions in use today with Arm and with mutual customers.  We will explain the requirements of hardware and software debugging and analysis for simulation, emulation and prototyping. In this presentation we will also showcase how Cadence’s verification solutions dovetail with Arm’s software tools to enable productive development and debug of the software stack in the context of the target hardware.

Our methodology team in collaboration with the Cadence® support team, developed an integrated approach utilizing the following Cadence verification tools: Palladium Z1, Interconnect Workbench and Perspec System Verifier.  The following significant improvements in efficiency were realized:  
    a)160x faster execution time
    b)2x-5x more efficient testbench creation
    c)4x-12x more efficient test pattern creation
We established a series of operational flows with AVIP ATP integrating IWB, Palladium, and Perspec. In the next phase, using the portable stimulus capability of Perspec, a mechanism to switch test patterns for models of TLM, RTL, or VIP will be supported in this environment.

This paper highlights the features of vManager and AMS used in our top level mixed signal DV environment, from our taped out designs in the past couple of years. Top Down Design and standardized test bench generation helped to streamline and create new test cases and checkers/asserts efficiently, in a relatively short time. Checkers/Asserts helped drastically to reduce the eye balling of waveforms between regressions, and deduct/list the issues in a trackable manner using vmanager interface. Randomization of input stimulus were done using simple system Verilog features which were integrated to the test bench environment to perform constraint random simulations. Regression results and metrics were mapped back to DV plan using vManager features to understand the gaps where tests needs to be extended and exercised.

This is a presentation we gave together with Texas Instruments, in last DVCon in Germany. Presenting a project done in Texas Instruments (Israel site) with the help of Cadence Perspec & Specman teams. The presentation drew much attention, won first prize in that event, and we want to use this opportunity to share it with the NA audience. The presentation explains the advantages of Persepc in generating stimuli, and shows the technical details of how it was done in TI project.

For an IP provider, there is always some risk in delivering verified IPs as any issue found within the IP can impact the SoC significantly. But when the IP is a feature rich and highly configurable SoC interconnect solution, the challenges of verifying and delivering a bug free IP gets compounded significantly. With traditional methods of verification getting overwhelmed by complex IPs such as these, companies such as Provino have adopted new methods to ensure their simulation resistant designs have zero bugs. This talk describes how formal sign-off was used to address this challenge and shares how simulation-resistant bugs were eradicated from the design, thereby considerably reducing the risks for the IP users.